FIG. 1 shows a block diagram for a conventional two-point modulator 10 which includes a phase lock loop (PLL) 12 that synthesizes a carrier frequency from a reference frequency (fref). The PLL 12 includes a voltage controlled oscillator (VCO) 20 generating a modulated frequency output signal (fout) having a central frequency which is set to the desired carrier frequency. The modulated frequency output signal fout is applied to the input of programmable divider (DIV) 22 which divides the modulated frequency output signal fout to generate a feedback frequency signal (ffb). A phase-frequency detector (PFD) 24 operates to compare the phase-frequency of the feedback frequency signal ffb to the phase-frequency of the reference frequency fref and generate a control signal 26 responsive to the phase-frequency difference. The control signal 26 drives the operation of a charge pump (CP) 28 to generate a control voltage signal 30. The control voltage signal 30 is filtered by a low pass filter (LPF) 32 and applied to the control input of the voltage controlled oscillator 20 as a voltage control signal (Vc). The frequency of the modulated frequency output signal fout generated by the voltage controlled oscillator 20 in response to the voltage control signal Vc is set as a function of the filtered control voltage signal 30.
The carrier frequency is determined by a digital control signal (fc) that is provided to an input of a sigma-delta (ΣΔ) modulator (SDM) 40 as a modulation control signal (Mc). The output of the sigma-delta modulator 40 is applied to a control input of the programmable divider 22 in order to set the average division ratio of the programmable divider 22. As an example, the output of the sigma-delta modulator 40 may be coded on one bit, with the logic value of this bit selecting the division ratio of either N or N+1, where N is an integer. Thus, the central frequency of the modulated frequency output signal fout is selectable between two values of N*fref and (N+1)*fref. If the output of the sigma-delta modulator 40 is instead coded on multiple bits, these bits will select one of several consecutive values for the central frequency of the modulated frequency output signal fout.
The two-point modulation is performed using two correlated modulation signals that respectively modulate: the filtered control voltage signal 30 setpoint at the output of the low pass filter 32 through modulation path (a), and the carrier frequency setpoint at the input of the sigma-delta modulator 40 through modulation path (b).
The digital data, also referred to in the art as the modulation data signal, is filtered by a transmit filter (TX-Filter) 50 (for example, a Gaussian filter). With respect to path (a), the filtered digital data 52 is converted by a modulation digital to analog converter (DAC) 54 to an analog voltage signal 56. An analog summation circuit 58 adds the analog voltage signal 54 to the filtered control voltage signal 30 for application to the input of the voltage controlled oscillator 20 as the voltage control signal (Vc). With respect to path (b), this filtered digital data 52 is added by a digital summation circuit 60 to the digital control signal fc for application to the input of the sigma-delta modulator 40 as the modulation control signal (Mc).
Those skilled in the art understand that the transfer function (Hb(s)) applied to the modulation seen from the programmable divider 22 through the operation of modulation path (b) exhibits a low pass behavior while the transfer function (Ha(s)) applied to the modulation seen from the digital to analog converter 54 through the operation of modulation path (a) exhibits a high pass behavior. If the sum of these two transfer functions is equal to a constant (i.e., Ha(s)+Hb(s)=1), then the bandwidth of the modulator 10 is infinite. This advantageous operating condition is achieved when the respective gains of the modulation paths (a) and (b) passing through the digital to analog converter 54 and programmable divider 22, respectively, are identical. If the gains are not matched, however, erroneous modulation of the modulated frequency output signal fout occurs.
Because the modulation path (b) is fully digital in nature, there is an inherent accuracy. The gain of modulation path (a), however, which is partially digital and partially analog, is inaccurate because the gain of the digital to analog converter 54 is process, voltage and temperature (PVT) dependent. To achieve gain matching, a calibration procedure is needed to offset this PVT dependence. In a common practice, for example before a transmit operation, the gain of the digital to analog converter 54 is calibrated (to match the path (b) gain) using a frequency lock loop (FLL) process. This calibration will not, however, address temperature variation. Additionally, the calibration process can take too long to complete (for example, not being able to be completed between channel switching operations when the two-point modulator is a component of an RF transceiver circuit).
There is accordingly a need in the art for a better calibration process which addresses some, or all, of the foregoing concerns.